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EM78452
8-Bit Microcontroller
Product Specification
DOC. VERSION 1.0
ELAN MICROELECTRONICS CORP.
October 2007
Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation.
Copyright (c) 2007 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 308 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Flat A, 19F., World Tech Centre 95 How Ming Street, Kwun Tong Kowloon, HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. 3F, SSMEC Bldg., Gaoxin S. Ave. I Shenzhen Hi-tech Industrial Park (South Area), Shenzhen CHINA 518057 Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA: Elan Information Technology Group (USA) P.O. Box 601 Cupertino, CA 95015 USA Tel: +1 408 366-8225 Fax: +1 408 366-8225
Shanghai: Elan Microelectronics Shanghai, Ltd. #23, Zone 115, Lane 572, Bibo Rd. Zhangjiang Hi-Tech Park Shanghai, CHINA 201203 Tel: +86 21 5080-3866 Fax: +86 21 5080-4600
Contents
Contents
1 2 3 4 5 General Description .................................................................................................. 1 Features ..................................................................................................................... 1 Pin Assignment ......................................................................................................... 2 Pin Description.......................................................................................................... 3 Function Description ................................................................................................ 4 5.1 Operational Registers......................................................................................... 4
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.1.8 5.1.9 5.1.10 5.1.11 5.1.12 5.1.13 5.1.14 5.1.15 R0 (Indirect Address Register) ............................................................................4 R1 (TCC) .............................................................................................................4 R2 (Program Counter) & Stack ...........................................................................4 R3 (Status Register) ............................................................................................6 R4 (RAM Select Register)...................................................................................6 R5~R8 (Port 5 ~ Port 8) ......................................................................................6 R9 (Port9)............................................................................................................7 RA (SPIRB: SPI Read Buffer) .............................................................................8 RB (SPIWB: SPI Write Buffer).............................................................................8 RC (SPIS: SPI Status Register) ..........................................................................8 RD (SPIC: SPI Control Register) ........................................................................9 RE (TMR1: Timer 1 Register)..............................................................................9 RF (PWP: Pulse Width Preset Register)...........................................................10 R20~R3E (General-purpose Register)..............................................................10 R3F (Interrupt Status Register) .........................................................................10 A (Accumulator).................................................................................................11 CONT (Control Register)...................................................................................11 IOC5 ~ IOC9 (I/O Port Control Register) ..........................................................11 IOCC (T1CON: Timer 1 Control Register).........................................................11 IOCD (Pull-high Control Register).....................................................................12 IOCE (WDT Control Register) ...........................................................................12 IOCF (Interrupt Mask Register).........................................................................13
5.2
Special Purpose Registers ............................................................................... 11
5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7
5.3 5.4 5.5
TCC/WDT Presacler......................................................................................... 15 I/O Ports ........................................................................................................... 15 Serial Peripheral Interface Mode...................................................................... 17
5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 Overview & Features.........................................................................................17 SPI Function Description...................................................................................19 SPI Signal & Pin Description.............................................................................21 Programmed the Related Registers..................................................................22 SPI Mode Timing ...............................................................................................25 Software Application of SPI ...............................................................................26
Product Specification (V1.0) 10.18.2007
* iii
Contents
5.6
Timer 1 ............................................................................................................. 30
5.6.1 5.6.2 5.6.3 Overview ...........................................................................................................30 Function Description..........................................................................................30 Programming the Related Registers .................................................................31 The Status of RST, T, and P of STATUS Register .............................................37
5.7 5.8 5.9
Reset and Wake-up.......................................................................................... 32
5.7.1
Interrupt ............................................................................................................ 38 Oscillator .......................................................................................................... 39
5.9.1 5.9.2 Oscillator Modes................................................................................................39 Crystal Oscillator/Ceramic Resonators (Crystal)...............................................39
5.10 Code Option Register :..................................................................................... 40 5.11 Instruction Set .................................................................................................. 41 6 7 5.12 Timing Diagrams .............................................................................................. 44 Absolute Maximum Rating ..................................................................................... 45 Electrical Characteristics ....................................................................................... 45 7.1 8 DC Characteristic ............................................................................................. 45 7.2 AC Characteristic ............................................................................................. 46 Application Circuit .................................................................................................. 47
APPENDIX
A B
Package Type: ......................................................................................................... 48 Package Information............................................................................................... 48 B.1 40-Lead Plastic Dual in line (PDIP) -- 600 mil ................................................. 48 B.2 44-Lead Quad Flat Package (QFP)................................................................. 49
Specification Revision History
Doc. Version 1.0 Revision Description Initial released version Date 2007/10/18
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Product Specification (V1.0) 10.18.2007
EM78452
8-Bit Microcontroller
1
General Description
The EM78452 is an 8-bit microprocessor designed and developed with low-power, high-speed CMOS technology. It has 4Kx13-bit on-chip ROM and 140x8-bit on-chip general purpose registers. Its operational kernel is implemented with RISC-like architecture and it is available in mask ROM version. The one time programmable (OTP) version is flexible, in both mass production and engineering test stages. OTP provides users with unlimited volume along with favorable price opportunities. This device is equipped with Serial Peripheral Interface (SPI) function, and it is suitable for wired communication. There are 58 easy-to-learn instructions and the user's program can be emulated with the EMC In-Circuit Emulator (ICE).
2
Features
CPU configuration * * * * * * * * * * * 4Kx13 bits on-chip ROM 140x8 bits on chip general purpose registers 11 special function registers 5-level stacks for subroutine nesting Serial Peripheral Interface (SPI) Four available interrupts: * * * * * * * External interrupt (/INT) SPI transmission completed interrupt TCC overflow interrupt Timer 1 overflow interrupt
Low power consumption: Less than 3 mA at 5V/4MHz Typically 10 A during sleep mode
Peripheral configuration 8-bit real time clock/counter (TCC) with overflow interrupt Power down mode I/O ports have Programmable wake-up function from sleep mode
I/O port configuration 5 bidirectional I/O ports (35 I/O pins) 12 Wake-up pins 32 programmable pull-high input pins 2 open-drain I/O pins 2 R-option pins
2 ~ 4 machine clocks for each instruction cycle 3 LED Direct sinking pins with internal serial resistors Built-in power-on reset Programmable free running on-chip watchdog timer Package Type: * * * 40-pin DIP 600mil 40-pin SOP 450mil 44-pin QFP : : : EM78452P EM78452WM EM78452AQ
Operating voltage range: 1.8V ~ 5.5V Operating temperature range: 0C ~70C Operating frequency range (base on two clocks): * Crystal mode: DC ~ 20MHz @ 5V DC ~ 16MHz @ 2.2V DC ~ 4MHz @ 1.8V
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
*1
EM78452
8-Bit Microcontroller
3
Pin Assignment
Vss /IN T DATA CLK P90 P 9 1 /S R D Y P 9 2 /S D I P 9 3 /S D O P 9 4 /S C K P 9 5 //S S P50 P51 P52 P53 P54 P55 P56 P57 P80 P81
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
OSCO R -O S C I VDD P 7 0 //R E S E T
P71 P72 P67 P66 P65 P64 P63 P61 P60 24 P62 P87 23 22 21 20 19 18 P86 P85 P84 P83 P82 NC P81 P80 P57 P56 P55 17 16 15 14 13 1 P90 2 P91/SRDY 3 P92/SDI 4 P93/SDO 5 P94/SCK 6 P95//SS 7 P50 8 P51 9 P52 10 P53 12 11 P54
P71 P72 P67
P70//RESET
33 34 35 36 37 38 39 40 41 42 43 44
32
31
30
29
28
27
26
25
Fig. 3-1a 40-pin DIP EM78452P
EM78452P
P66
NC
P65
NC
P64
NC
P63
VDD
P62
R-OSCI
P61
OSCO
EM 78452AQ
P60
Vss
P87
/INT
P86 P85
DATA CLK
P84 P83 P82
Fig. 3-1b 44-pin QFP EM78452AQ Fig. 3-1 Pin Assignment
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Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
4
Pin Description
Symbol P50~P57 P60~P67 P70~P72 Pin No. 11~18 27~34 37~35 Type I/O I/O I/O Function Description 8-bit bidirectional general-purpose I/O port. All of its pins can be pulled-high individually by software. 8-bit bidirectional general-purpose I/O port. All of its pins can be pulled-high by software, and pin-change wake-up pins. LED direct-driving pins with internal serial resistor used as output and is software defined. 8-bit bidirectional general-purpose I/O port. All of its pins can be pulled-high by software. P80 and P81 are also used as R-option pins. 6-bit bidirectional general-purpose I/O port. All of its pins can be pulled-high by software. P90 and P91 are pin-change wake-up pins. LED direct-driving pin with internal serial resistor used as output and is software defined. P70/ RESET Code option Bit 3 (REN): reset enable 37 I/O REN=0 for reset pin REN=1 for general purpose I/O (P70) Internal pull high resistor 220K R-OSCI OSCO 39 40 I O Crystal input Crystal output By connecting P74 and P76 together, P74 can be pulled-high by software and it is also a pin-change wake-up pin. P76 can be defined as an open-drain output. DATA VDD VSS /INT SRDY SDI SDO SCK /SS 3 38 1 2 6 7 8 9 10 I/O - - I I/O I/O I/O I/O I/O By connecting P75 and P77 together, P75 can be pulled-high by software and it is also a pin-change wake-up pin. P77 can be defined as an open-drain output. Power supply pin Ground pin Interrupt Schmitt trigger pin. The interrupt function is triggerred at a falling edge. Users can enable it by software. Slave Ready pin for SPI Serial data in for SPI Serial data out for SPI Serial clock for SPI /Slave select for SPI
P80~P87
19~26
I/O
P90~P95
5~10
I/O
CLK
4
I/O
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
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EM78452
8-Bit Microcontroller
5
Function Description
WDT Timer
WDT Time-out
PC
STACK 1 STACK 2 STACK 3
Prescaler
Oscillator/ Timming Control
/ INT
Interrupt Control
ROM
Instruction Register
STACK 4 STACK 5
R1(TCC)
Sleep & Wake Up Control
ALU RAM
R4 Instruction Decoder R3 ACC TMR1
DATA & CONTROL BUS
IOC5 R5
PPPPPPPP 55555555 01234567
IOC6 R6
PPPPPPPP 66666666 01234567 P 7 0
IOC7 R7
P 7 1 P 7 2
IOC8 R8
PPPPPPPP 88888888 01234567
IOC9 R9
PP PP 9999 0123 /// S SS R DD DI O Y P 9 4 / S C K P 5 5 / / S S
SPI ENGIN
Fig. 5-1 Functional Block Diagram
5.1 Operational Registers
5.1.1 R0 (Indirect Address Register)
R0 is not a physically implemented register. It is used as an indirect addressing pointer. Any instruction using R0 as register actually accesses data pointed by the RAM Select Register (R4).
5.1.2 R1 (TCC)
R1 is incremented by the instruction cycle clock. It is written and read by the program as any other register.
5.1.3 R2 (Program Counter) & Stack
R2 and the hardware stacks are 12 bits wide. The structure is depicted in Fig. 5-2. Generates 4K x 13 on-chip ROM addresses to the relative programming instruction codes. One program page is 1024 words long. All the R2 bits are set to "1"s as a reset condition occurs.
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Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows it to jump to any location on one page. "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page "RET" ("RETL k", "RETI") instruction loads the program counter with the contents at the top of the stack. "MOV R2, A" allows the loading of an address from the "A" register to the lower 8 bits of PC, and the ninth and tenth bits (A8~A9) of the PC are cleared. "ADD R2, A" allows a relative address to be added to the current PC, and the ninth and tenth bits of the PC are cleared. Any instruction that is written to R2 (e.g. "ADD R2, A", "MOV R2, A", "BC R2,6",) (except "TBL") will cause the ninth and tenth bits (A8~A9) of the PC to be cleared. Thus, the computed jump is limited to the first 256 locations of any program page. "TBL" allows a relative address to be added to the current PC (R2+AR2), and contents of the ninth and tenth bits (A8~A9) of the PC are not changed. Thus, the computed jump can be on the second (or third, 4th) 256th locations on one program page. In the case of EM78452, the most significant bits (A10~A11) will be loaded with the contents of bits PS0~PS1 in the status register (R3) upon the execution of a "JMP", "CALL", or any other instructions which writes to R2. All instructions are single instruction cycle (fclk/2 or fclk/4 except for instructions that would change the contents of R2. Such instruction will need one more instruction cycle.
R3
000H 001H 002H
A11 A10 A9 A8
A7 CALL RET RETL RETI
~
A0
Hardware Vector Software Vector
User Memory Space
00 PAGE0 0000~03FF 01 PAGE1 0400~07FF 10 PAGE2 0800~0BFF 11 PAGE3 0C00~0FFF
Stack Level 1 Stack Level 2 Stack Level 3 Stack Level 4 Stack Level 5
On-chip Program Memory
Reset Vector
FFFH
Fig. 5-2 Program Counter Organization
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
*5
EM78452
8-Bit Microcontroller
5.1.4 R3 (Status Register)
Bit 7 GP Bit 6 PS1 Bit 5 PS0 Bit 4 T Bit 3 P Bit 2 Z Bit 1 DC Bit 0 C
Bit 7 (GP): General read/write bit. Bits 6 ~ 5 (PS1 ~ PS0): Page select bits. PS0~PS1 are used to pre-select a program memory page. When executing a "JMP", "CALL", or other instructions which causes the program counter to be changed (e.g. MOV R2, A), PS0~PS1 are loaded into the 11th and 12th bits of the program counter where it selects one of the available program memory pages. Note that RET (RETL, RETI) instruction does not change the PS0~PS1 bits. For this reason, the return will always be to the page from where the subroutine was called, regardless of the current settings of PS0~PS1 bits. PS1 bit is not used (read as "0") and cannot be modified in EM78452.
PS1 0 0 1 1 PS0 0 1 0 1 Program Memory Page [Address] Page 0 [000-3FF] Page 1 [400-7FF] Page 2 [800-BFF] Page 3 [C00-FFF]
Bit 4 (T): Time-out bit. Set to "1" with the "SLEP" and the "WDTC" commands, or during power up and reset to "0" with the WDT timeout. Bit 3 (P): Power down bit. Set to "1" during power on or by a "WDTC" command and reset to "0" by a "SLEP" command. Bit 2 (Z): Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. Bit 1 (DC): Auxiliary carry flag Bit 0 (C): Carry flag
5.1.5 R4 (RAM Select Register)
Bits 7~6: determines which bank is activated among the 4 banks. Bits 5~0: are used to select the registers (Address: 00~3F) in the indirect addressing mode. If indirect addressing is not used, the RSR is used as an 8-bit general-purpose read/writer register. See the data memory configuration in Fig. 5-3.
5.1.6 R5~R8 (Port 5 ~ Port 8)
Four general 8 bits I/O registers
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Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
Both P74 and P76 reads or writes data from the DATA pin, while both P75 and P77 reads or writes data from the CLK pin.
5.1.7 R9 (Port9)
The general 6-bit I/O register. The values of the two most significant bits are read as "0".
Address
R PAGE registers
IOC PAGE registers
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 1F 20 3E
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE
(Indirect Addressing Register) (Time Clock Counter) (Program Counter) (Status Register) (RAM Select Register) (Port5) (Port6) (Port7) (Port8) (Port9) (SPI read buffer) (SPI write buffer) (SPI status buffer) (SPI control buffer) (Timer1 register) Reserve
Reserve CONT (Control Register) Reserve Reserve Reserve IOC5 (I/O Port Control Register) IOC6 (I/O Port Control Register) IOC7 (I/O Port Control Register) IOC8 (I/O Port Control Register) IOC9 (I/O Port Control Register) Reserve Reserve IOCC (Timer1 Control Register) IOCD (Pull_high Control Register) IOCE (WDT Control Register) IOCF (Interrupt Mask Register)
General Registers
Bank0
Bank1
Bank2
Bank3
3F
R3F
(Interrupt Status Register)
Fig. 5-3 Data Memory Configuration
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
*7
EM78452
8-Bit Microcontroller
5.1.8 RA (SPIRB: SPI Read Buffer)
Address 0X0A Name SPIRB/RA Bit 7 SRB7 Bit 6 SRB6 Bit 5 SRB5 Bit 4 SRB4 Bit 3 SRB3 Bit 2 SRB2 Bit 1 SRB1
SRB7~SRB0 are the 8-bit data when transmission is completed by SPI.
5.1.9 RB (SPIWB: SPI Write Buffer)
Address 0x0B Name Bit 7 Bit 6 SWB6 Bit 5 SWB5 Bit 4 SWB4 Bit 3 Bit 2 Bit 1 Bit 0 SPIWB/RB SWB7 SWB3 SWB2 SWB1 SWB0
SWB7~SWB0 are the 8-bit data that are waiting for transmission by SPI.
5.1.10 RC (SPIS: SPI Status Register)
Address Name 0x0C Bit 7 Bit 6 TD1 Bit 5 TD0 Bit 4 TM1IF Bit 3 OD3 Bit 2 OD4 Bit 1 Bit 0 RBF
SPIS/RC DORD
Bit 7 (DORD): Data transmission order. 0 : Shift left (MSB first) 1 : Shift right (LSB first) Bit 6~Bit 5: SDO Status output Delay times Options
TD1 0 0 1 1 TD0 0 1 0 1 Delay Time 8 CLK 16 CLK 24 CLK 32 CLK
Bit 4 (T1ROS): Timer 1 Read Out Buffer Select Bit 0 : Read Value from Timer 1 Preset Register 1 : Read Value from Timer 1 Counter Register Bit 3 (OD3): Open-Drain Control bit 0 : Open-drain disable for SDO 1 : Open-drain enable for SDO Bit 2 (OD4): Open-Drain Control bit 0 : Open-drain disable for SCK 1 : Open-drain enable for SCK Bit 1: not used, read as "0"
Bit 0 (RBF): Read Buffer Full flag 0 : Receiving not completed, and SPIRB has not fully exchanged. 1 : Receiving completed; SPIRB is fully exchanged.
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Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
5.1.11 RD (SPIC: SPI Control Register)
Address 0x0D Name SPIC/RD Bit 7 CES Bit 6 SPIE Bit 5 SRO Bit 4 SSE Bit 3 Bit 2 Bit 1 Bit 0 SDOC SBRS2 SBRS1 SBRS0
Bit 7 (CES): Clock Edge Select bit 0 : Data shifts out on a rising edge, and shifts in on a falling edge. Data is on hold during low-level. 1 : Data shifts out on a falling edge, and shifts in on a rising edge. Data is on hold during high-level. Bit 6 (SPIE): SPI Enable bit 0 : Disable SPI mode 1 : Enable SPI mode Bit 5 (SRO): SPI Read Overflow bit 0 = No overflow 1 = A new data is received while the previous data is still being held in the SPIB register. In this situation, the data in the SPIS register will be destroyed. To avoid setting this bit, users are required to read the SPIRB register although only the transmission is implemented. Note that this can only occur in slave mode. Bit 4 (SSE): SPI Shift Enable bit 0 = Reset as soon as shifting is completed, and the next byte is ready to be shifted. 1 = Start to shift, and keep at "1" while the current byte is still being transmitted. It should be noted that this bit will be reset to 0 at every 1-byte transmission by the hardware. Bit 3 (SDOC): SDO output status control bit: 0 : After the Serial data output, the SDO remains high. 1 : After the Serial data output, the SDO remains low. Bit 2~Bit 0 (SBRS): SPI Baud Rate Select bits Refer to the SPI baud rate table illustration under the section "SPI" on the subsequent pages.
5.1.12 RE (TMR1: Timer 1 Register)
Address 0X0E Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR1/RE TMR17 TMR16 TMR15 TMR14 TMR13 TMR12 TMR11 TMR10
TMR17~TMR10 are the set of bits of Timer 1 register and such are incremented until the value matches PWP and then it resets to 0.
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
*9
EM78452
8-Bit Microcontroller
5.1.13 RF (PWP: Pulse Width Preset Register)
Address Name 0x0F Bit 7 Bit 6 PWP6 Bit 5 PWP5 Bit 4 PWP4 Bit 3 PWP3 Bit 2 PWP2 Bit 1 PWP1 Bit 0 PWP0 PWP/RF PWP7
PWP7~PWP0 are the set of bits with pulse width preset in advance for the desired width of the baud clock.
5.1.14 R20~R3E (General-purpose Register)
RA~R1F, and R20~R3E (including Banks 0~3) are general-purpose registers.
5.1.15 R3F (Interrupt Status Register)
Address Name 0x3F ISR/R3F Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 TM1IF Bit 2 SPIIF Bit 1 EXIF Bit 0 TCIF
Bits 7~4: not used, read as "0". Bit 3 (TM1IF): Timer 1 interrupt flag. Set by the comparator at Timer 1 application, flag is cleared by software. Bit 2 (SPIIF): SPI interrupt flag. Set during data transmission completed, flag is cleared by software. Bit 1 (EXIF): External interrupt flag. Set by a falling edge on the /INT pin, flag is cleared by software Bit 0 (TCIF): TCC overflow interrupt flag. Set as TCC overflows; flag is cleared by software. 0 : means no interrupt occurs 1 : means with interrupt request R3F can be cleared by instruction, but cannot be set by instruction. IOCF is the interrupt mask register. Note that when reading R3F it will result to "logic AND" of R3F and IOCF.
PSR2 0 0 0 0 1 1 1 1 PSR1 0 0 1 1 0 0 1 1 PSR0 0 1 0 1 0 1 0 1 TCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 WDT Rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
10 *
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
5.2 Special Purpose Registers
5.2.1 A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator, which is not an addressable register.
5.2.2 CONT (Control Register)
Bit 7 /PHEN Bit 6 /INT Bit 5 Bit 4 Bit 3 PAB Bit 2 PSR2 Bit 1 PSR1 Bit 0 PSR0
Bit 7 (/PHEN) I/O pin pull-high enable flag. 0: For P60~P67, P74~P75 and P90~P95, the pull-high function is enabled. 1: The pull-high function is disabled. Bit 6 (INT) An interrupt enable flag cannot be written to by the CONTW instruction. 0: interrupt masked by the DISI instruction. 1: interrupt enabled by the ENI or RETI instruction. Bits 5 and 4: Not used, read as "0". Bit 3 (PAB) Prescaler assignment bit. 0: TCC 1: WDT Bit 2 (PSR2) ~ Bit 0 (PSR0) TCC/WDT prescaler bits. Bits 0~3, and 7 of the CONT register are readable and writable.
5.2.3 IOC5 ~ IOC9 (I/O Port Control Register)
0: puts the relative I/O pin as output 1: puts the relative I/O pin into high impedance Both P74 and P76 should not be defined as output pins at the same time. This also applies to both P75 and P77. Only the lower 6 bits of the IOC9 register are used.
5.2.4 IOCC (T1CON: Timer 1 Control Register)
Address 0x0C Name
T1CON/IOCC
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 TM1E
Bit 1
Bit 0
TM1P1 TM1P0
Bit 2 (TM1E): Timer 1 Function Enable bit 0 : Disable Timer 1 function as default 1 : Enable Timer 1 function Bit 1~Bit 0 (TM1P): Timer 1 Prescaler bit
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
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EM78452
8-Bit Microcontroller
Refer to the Timer 1 prescaler table for FOSC illustration under the section "Timer 1" on the subsequent pages.
5.2.5 IOCD (Pull-high Control Register)
Bit 7 S7 Bit 6 Bit 5 Bit 4 Bit 3 /PU9 Bit 2 /PU8 Bit 1 /PU6 Bit 0 /PU5
The default values of /PU5, /PU6, /PU8, and /PU9 are "1", which means that the pull-high function is disabled. /PU6 and /PU9 are "AND" gating with /PHEN, that is, when each one is written with a "0", pull high is enabled. S7 defines the driving ability of the P70-P72. 0: Normal output 1: Enhances the driving ability of the LED
5.2.6 IOCE (WDT Control Register)
Bit 7 Bit 6 ODE Bit 5 WDTE Bit 4 SLPC Bit 3 ROC Bit 2 Bit 1 Bit 0 /WUE
Bits 7, and 1~2 are not used. Bit 6 (ODE) Open-drain control bit. 0 : Both P76 and P77 are normally I/O pins. 1 : Both P76 and P77 pins have the open-drain function inside. The ODE bit can be read and written to. Bit 5 (WDTE) Control bit used to enable the Watchdog timer. The WDTE bit can be used only if ENWDT, the Code Option bit, is "1." If the ENWDT bit is "1," then WDT can be disabled / enabled by the WDTE bit. 0: Disable WDT 1: Enable WDT The WDTE bit is not used if ENWDT, the Code Option bit ENWD is "0". That is, if the ENWDT bit is "0", WDT is always disabled no matter what the WDTE bit is. The WDTE bit can be read and written to. Bit 4 (SLPC) This bit is set by hardware at a falling edge of the wake-up signal and is cleared by software. The SLPC is used to control the oscillator operation. The oscillator is disabled (oscillator stops, and the controller enters the Sleep 2 mode) on the high-to-low transition and is enabled (the controller is awakened from Sleep 2 mode) on a low-to-high transition.
12 * Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
In order to ensure a stable output of the oscillator, once the oscillator is enabled again, there is a delay of approximately 18 ms (oscillator start-up timer (OST)) before the next program instruction is executed. The OST is always activated by wake-up from sleep mode whether the Code Option bit ENWDT is "0" or not. After waking up, the WDT is enabled if the Code Option ENWDT is "1". The block diagram of Sleep 2 mode and wake-up caused by the input trigger is depicted in Fig. 5-4. The SLPC bit can be read and written to. Bit 3 (ROC) ROC is used for the R-option. Setting ROC to "1" will enable the status of the R-option pins (P80, P81) to be read by the controller. Clearing ROC will disable the R-option function. Otherwise, the R-option function is introduced. Users must connect the P81 pin and/or P80 pin to VSS by a 560K external resistor (Rex). If Rex is connected/disconnected with VDD, the status of P80 (P81) will be read as "0"/"1" (refer to Fig. 7(b)). The ROC bit can be read and written to. Bit 0 (/WUE) This control bit is used to enable the wake-up function of P60~P67, P74~P75, and P90~P91. 0 : Enable the wake-up function 1 : Disable the wake-up function The /WUE bit can be read and written to.
5.2.7 IOCF (Interrupt Mask Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 TM1IE Bit 2 SPIIE Bit 1 EXIE Bit 0 TCIE
Bits 4~7 Not used. Individual interrupt is enabled by setting its associated control bit in IOCF to "1". The IOCF Register could be read and written to. Bit 3 (TM1IE) TM1IE interrupt enable bit. 0 : disable TM1IE interrupt 1 : enable TM1IE interrupt Bit 2 (SPIIE) SPI interrupt enable bit. 0 : disable SPI interrupt 1 : enable SPI interrupt Bit 1 (EXIE) EXIF interrupt enable bit. 0 : disable EXIF interrupt 1 : enable EXIF interrupt Bit 0 (TCIE) TCIF interrupt enable bit. 0 : disable TCIF interrupt 1: enable TCIF interrupt
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
* 13
EM78452
8-Bit Microcontroller
/W U E
O s c illa to r
E n a b le D is a b le R eset
P D R CLK C L
/W U E
Q Q
VCC
C le a r
Set
8
/W U E
fr o m S /W
P60~P67
VCC
/W U E /P H E N 4
P74~P75, P90~P91
Fig. 5-4 Block Diagram of Sleep Mode and Wake-up Circuits on the I/O Ports
14 *
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
5.3 TCC/WDT Presacler
An 8-bit counter is available as prescaler for the TCC or WDT. The prescaler is available for either the TCC or WDT at any given time, and the PAB bit of CONT register is used to determine the prescaler assignment. The PSR0~PSR2 bits determine the prescaler ratio. The prescaler is cleared each time the instruction is written to TCC in TCC mode. The WDT and prescaler, when assigned to WDT mode, are cleared by the WDTC or SLEP instructions. Fig. 5-5 depicts the circuit diagram of TCC/WDT. R1 (TCC) is an 8-bit timer/counter. TCC will increase by one at every instruction cycle (without prescaler). The watchdog timer is a free running on-chip RC oscillator. The WDT will keep running even when the oscillator driver has been turned off (i.e. in sleep mode). During normal or sleep mode operation, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any time during normal mode by software programming (if Code Option bit ENWDT is "1"). Refer to the WDTE bit of the IOCE register. Without presacler, the WDT time-out period is approximately 18 ms 1.
5.4 I/O Ports
The I/O registers, from Port 5 to Port 9, are bidirectional tri-state I/O ports. P60~P67, P74~P75, and P90~P91 provides internal pull-high. P60~P67, P74~P75, and P90~P95 provides programmable wake-up function through software. P76~P77 can have an open-drain output by software control. P80~P81 are the R-option pins which are enabled by software. When the R-option function is used, it is recommended that P80 and P81 be used as output pins. During R-option enabled state, P80 and P81 must be programmed as input pins. If an external resistor is connected to P80 (P81) for the R-option function, the current consumption should be taken as an important factor in the applications for low power consideration. The I/O ports can be defined as "input" or "output" pins by the I/O control registers (IOC5~IOC9) under program control. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuit is shown in Fig. 5-6. Note that the reading path source of input and output pins is different when reading the I/O port.
1
Vdd = 5V, set up time period = 16.2ms 30% Vdd = 3V, set up time period = 18.0ms 30%
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
* 15
EM78452
8-Bit Microcontroller
CLK(=Fosc/2)
Data Bus
1
M U X
0
SYNC 2 cycles
TCC(R1)
PAB
0
TCC overflow interrupt
WDT
1
M U X
8-bit Counter PSR0~PSR2 8 - to -1 MUX
0 1
WDTE (in IOCE)
MUX
PAB
WDT timeout
Fig. 5-5 Block Diagram of TCC WDT
PCRD
Q
PD R CLK QC L
PCWR
PORT
Q
P RD C CLK QL
IOD PDWR
0 1
M U X
PDRD
Fig. 5-6 (a) I/O Port and I/O Control Register Circuit
16 *
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
PCRD VCC ROC
Q P D R CLK C L
W eakly Pull-up
PCWR
Q
PORT
Q Q
P D R C CLK L
IOD PDWR
0 Rex* 1
M U X
PDRD
*The Rex is 560K ohm external resistor
Fig. 4-6(b) The Circuit of I/O Port with R-option (P80, P81)
5.5 Serial Peripheral Interface Mode
5.5.1 Overview & Features
Overview:
Figures 4-7, 4-8, and 4-9 shows how the EM78452 communicates with other devices through SPI module. If EM78452 is a master controller, it sends clock through the SCK pin. A couple of 8-bit data are transmitted and received at the same time. However, if EM78452 is defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to be shifted based on both the clock rate and the selected edge. In Slave mode when code option bit 7 (SPIHSK) is set to 0, the P91 (HSK) pin will be set to high after SPI enable and SSE bit set to 1. You can also set SPIS bit 7(DORD) to decide the SPI transmission order, SPIC bit3 (SDOC) to control SDO pin after serial data output status and SPIS bit 6 (TD1), bit 5 (TD0) decides the SDO status output delay times. Those three functions mentioned can work however; it must be based on code option bit5 (SDOS) set to 0.
Features:
Operation in either Master mode or Slave mode Three-wire or four-wire synchronous communication; that is, full duplex Programmable baud rates of communication Programming clock polarity, (RD bit7) Interrupt flag available for the read buffer full SPI transmission order
* 17
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
After serial data output SDO status select SDO status output delay times SPI handshake pin Up to 8 MHz (maximum) bit frequency
SDO SPIR Reg SPIW SPIW Reg Reg /SS SPIS Reg Bit 7 Master Device SCK Slave Device SDI SPI Module SPIR Reg SPIW SPIW Reg Reg
Fig. 5-7 SPI Master/Slave Communication
SDI SDO SCK /SS
Vdd Master
P50 P51 P52 P53
SDO SDI SCK /SS
SDO SDI SCK /SS
Slave Device 1
SDO SDI SCK /SS
SDO SDI SCK /SS
Slave Device 2
Slave Device 3
Slave Device 4
Fig. 5-8 SPI Configuration of Single-Master and Multi-Slave
18 *
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
SDI SDO SCK /SS Master 1 or Slave 1
SDI SDO SCK /SS Master 2 or P50 Slave 6 P51 P52 P53
P50 P51 P52 P53
Slave 2 for Master 1
5.5.2 SPI Function Description
SDO SDI SCK /SS
R ead
RBF S e t to 1 RBFI
Slave 3 for Master 1 or Master 2
Fig. 5-9 SPI Configuration of Single-Master and Multi-Slave
SDO SDI SCK /SS
W rite
Slave 4 for Master 1 or Master 2
SDO SDI SCK /SS
Slave 5 for Master 2
SDO SDI SCK /SS
S P IR
re g
SE
S P IW
re g
B u ffe r F u ll D e te c to r
S P IS
P 9 2 /S D I
b it 0
re g
s h ift rig h t
b it 7
S P IC re g P 9 3 /S D O
Edge S e le c t
SB R 0 ~SB R 2
P 9 5 / /S S
/ SS
T sco
SB R 2~SB R 0 8
C lo c k S e le c t 2
N o is e F ilte r
P re sc a ler 4, 8 , 1 6 , 3 2 , 64
Edge S e le c t
T M R 1 /2 S P IC b it6
P 9 4 /S C K
Fig. 5-10 SPI Block Diagram
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
* 19
EM78452
8-Bit Microcontroller
SPI
SPI Write Register (0X0B)
/SS
SPI Read Register (0X0A)
SDO
SDI Shift Clock
SPI Mode Select Register
20 *
210 SPIC
Below are the functions of each block and explanations on how to carry out the SPI communication with the signals depicted in Fig.4-10 and Fig.4-11: P91/SRDY : Slave Ready pin P92/SDI : Serial Data In P93/SDO : Serial Data Out P94/SCK : Serial Clock P95//SS:/Slave Select (Option). This pin (/SS) may be required during slave mode. RBF : Set by Buffer Full Detector, and reset by software. Buffer Full Detector : Set to 1 when an 8-bit shifting is completed. SSE : Loads the data in SPIS register, and begin to shift SPIS reg. : Shifting byte in and out. The MSB is shifted first. Both the SPIS and the SPIW registers are loaded at the same time. Once data are written, SPIS starts transmission / reception. The data received will be moved to the SPIR register as the shifting of the 8-bit data is completed. The RBF (Read Buffer Full) flag and the RBFI (Read Buffer Full Interrupt) flag are then set. SPIR reg. : Read buffer. The buffer will be updated as the 8-bit shifting is completed. The data must be read before the next reception is completed. The RBF flag is cleared as the SPIR register reads. SPIW reg. : Write buffer. The buffer will deny any attempts to write until the 8-bit shifting is completed.
8-1 MUX
SPI Shift Buffer
FOSC
7~0 SPIWB
10 764 10 T1CON SPIC SPIS DATA BUS
2 INTC
4 SPIC
7~0 SPIRB
Fig. 5-11 The Function Block Diagram of SPI Transmission
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
The SSE bit will be kept in "1" if the communication is still undergoing. This flag must be cleared as the shifting is completed. Users can determine if the next write attempt is available. SBRS2~SBRS0: Programming the clock frequency/rates and sources. Clock Select:Selects either the internal or the external clock as the shifting clock. Edge Select: Selects the appropriate clock edges by programming the CES bit
5.5.3 SPI Signal & Pin Description
The detailed functions of the four pins, SDI, SDO, SCK, and /SS, which are shown in Fig. 5-8.
SRDY/P92 (Pin 6):
Slave ready pin In Slave mode when code option bit 7 (SPIHSK) set to 0, P91 (SRDY) this pin will be set to high after SPI enable and SSE bit set to 1.
SDI/P92 (Pin 7):
Serial Data In, Receive sequentially, the Most Significant Bit (MSB) first, Least Significant Bit (LSB) last, Defined as high-impedance, if not selected, Program the same clock rate and clock edge to latch on both the master and slave devices, The byte received will update the transmitted byte, Both the RBF and RBFIF bits (located in Register 0x0C) will be set as the SPI operation is completed. Timing is shown in Fig. 5-12 and 5-13.
SDO/P93 (Pin 8):
Serial Data Out, Transmit sequentially; the Most Significant Bit (MSB) first, Least Significant Bit (LSB) last, Program the same clock rate and clock edge to latch on both the master and slave devices, The received byte will update the transmitted byte, The CES (located in Register 0x0D) bit will be reset, as the SPI operation is completed. Timing is shown in Fig. 5-12 and 5-13.
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
* 21
EM78452
8-Bit Microcontroller
SCK/P94 (Pin 9):
Serial Clock Generated by a master device Synchronize the data communication on both the SDI and SDO pins The CES (located in Register 0x0D) is used to select the edge to communicate. The SBR0~SBR2 (located in Register 0x0D) is used to determine the baud rate of communication The CES, SBR0, SBR1, and SBR2 bits have no effect in slave mode Timing is shown in Fig. 5-12 and Fig. 5-13
/SS/P95 (Pin 10):
Slave Select; negative logic Generated by a master device to signify the slave(s) to receive data Goes low before the first cycle of SCK appears, and remains low until the last (eighth) cycle is completed Ignores the data on the SDI and SDO pins while /SS is high, because the SDO is no longer driven. Timing is shown in Fig. 5-12 and Fig. 5-13.
5.5.4 Programmed the Related Registers
As the SPI mode is defined, the related registers of this operation are shown in Table 2 and Table 3. Table 1 Related Control Registers in SPI Mode
Address
0x0D 0x0F
Name
*SPIC/RD INTC/IOCF
Bit 7
CES --
Bit 6
SPIE --
Bit 5
SRO --
Bit 4
SSE --
Bit 3
SDOC TM1IE
Bit 2
SBR2 SPIIE
Bit 1
SBR1 EXIE
Bit 0
SBR0 TCIE
SPIC: SPI Control Register. Bit 7 (CES): Clock Edge Select bit 0 : Data shifts out on rising edge, and shifts in on falling edge. Data is on hold during the low level. 1 : Data shifts out on falling edge, and shifts in on rising edge. Data is on hold during the high level.
22 *
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
Bit 6 (SPIE): SPI Enable bit 0 : Disable SPI mode 1 : Enable SPI mode Bit 5 (SRO): SPI Read Overflow bit 0 : No overflow. 1 : A new data is received while the previous data is still being on hold in the SPIB register. Under this condition, the data in the SPIS register will be destroyed. To avoid setting this bit, users should read the SPIRB register even if the transmission is implemented only. Note that this can only occur in slave mode. Bit 4 (SSE): SPI Shift Enable bit 0 : Reset as soon as the shifting is completed and the next byte is ready to shift. 1 : Start to shift, and stays on 1 while the current byte continues to transmit. Note that this bit can be reset by hardware only. Bit 3 (SDOC): SDO output status control bit: 1 : After Serial data output SDO keep low. 0 : After Serial data output SDO keep High Bits 2~0 (S BRS): SPI Baud Rate Select Bits
SBRS2 (Bit 2) 0 0 0 0 1 1 1 1 SBRS1 (Bit 1) 0 0 1 1 0 0 1 1 SBRS0 (Bit 0) 0 1 0 1 0 1 0 1 Mode Master Master Master Master Master Slave Slave Master Baud Rate Fosc/2 Fosc/4 Fosc/8 Fosc/16 Fosc/32 /SS enable /SS disable TMR1/2
Note: In Mater mode, the /SS pin is disabled.
INTC: Interrupt control register Bit 3 (TM1IE) TM1IE interrupt enable bit. 0 : disable TM1IE interrupt 1 : enable TM1IE interrupt
* 23
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
Bit 2 (SPIIE) SPI interrupt enable bit. 0 : disable SPI interrupt 1 : enable SPI interrupt Bit 1 (EXIE) EXIF interrupt enable bit. 0 : disable EXIF interrupt 1 : enable EXIF interrupt Bit 0 (TCIE) TCIF interrupt enable bit. 0 : disable TCIF interrupt 1 : enable TCIF interrupt
Table 2 Related Status/Data Registers of the SPI Mode
Address 0X0A 0x0B 0x0C Name Bit 7 Bit 6 SRB6 SWB6 TD1 Bit 5 SRB5 SWB5 TD0 Bit 4 SRB4 SWB4 TM1IF Bit 3 SRB3 SWB3 OD3 Bit 2 SRB2 SWB2 OD4 Bit 1 Bit 0
SPIRB/RA SRB7 SPIWB/RB SWB7 SPIS/RC DORD
SRB1 SRB0 SWB1 SWB0 RBF
SPIRB:
SPI Read Buffer. Once the serial data is received completely, it will be loaded to SPIRB from SPISR. The RBF bit and the RBFIF bit in the SPIS register will also be set. SPI Write Buffer. As transmitted data is loaded, the SPIS register stands by and start to shift the data when sensing SCK edge with SSE set to "1".
SPIWB:
SPIS: SPI Status register Bit 7 (DORD): Read Buffer Full Interrupt flag 0 : Shift left (MSB first) 1 : Shift right (LSB first) Bit 6~Bit 5: SDO Status Output Delay Times Options
TD1 0 0 1 1 TD0 0 1 0 1 Delay Time 8 CLK 16 CLK 24 CLK 32 CLK
24 *
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
T1ROS (Bit 4): Timer 1 Read Outbuffer Select Bit 0 : Read Value from Timer 1 Preset Register 1 : Read Value from Timer 1 Counter Register Bit 4 (TM1IF): Timer 1 interrupt flag Bit 3 (OD3) Open-Drain Control bit (P93) 0 : Open-drain disable for SDO 1 : Open-drain enable for SDO Bit 2 (OD4): Open Drain-Control bit (P94) 0 : Open-drain disable for SCK 1 : Open-drain enable for SCK Bit 0 (RBF): Read Buffer Full flag 0 = Receive is ongoing, SPIB is empty. 1 = Receive is completed, SPIB is full.
5.5.5 SPI Mode Timing
The edge of SCK is selected by programming bit CES. The waveform shown in Fig. 5-12 is applicable regardless whether the EM78452 is in master or slave mode with /SS disabled. However, the waveform in Fig. 5-13 can only be implemented in slave mode with /SS enabled.
Fig. 5-12 SPI Mode with /SS Disabled
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
* 25
EM78452
8-Bit Microcontroller
Fig. 4-13 SPI Mode with /SS Enable
5.5.6 Software Application of SPI
Example for SPI: For Master ORG 0X0
Setting:
CLRA IOW 0X05 IOW 0X06 MOV 0X05,A MOV A,@0B11001111 CONTW MOV A,@0B00010001 IOW 0X0E MOV A,@0B00000000 IOW 0X0F MOV A,@0x07 IOW 0x09 MOV A,@0B10000000 MOV 0x0C,A MOV A,@0B11100000 MOV 0X0D,A
; Set Port 5 output ; Set Port 6 output ; Set prescaler for WDT ; Disable wake-up function ; Disable interrupt ; SDI input and SDO, SCK output ; Clear RBF and RBFIF flag ; Select clock edge and enable SPI
26 *
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
Start:
WDTC BC 0X0C,1 MOV A,@0XFF MOV 0X05,A MOV 0X0A,A MOV A,@0XAA MOV 0X0B,A BS 0X0D,4 NOP JMP SETTING JMP $-2 BC 0X03,2 CALL DELAY MOV A,0X0A XOR A,@0X5A JBS 0X03,2 JMP START FLAG: MOV A,@0X55 MOV 0X05,A CALL DELAY JMP START DELAY:
; Clear RBFIF flag ; Show a signal at Port 5 ; Move FF at read buffer ; Move AA at write buffer ; Start to shift SPI data ; Polling loop for checking SPI ; transmission completed ; To catch the data from slaver ; Compare the data from slaver
; Show the signal when receiving ; correct data from slaver
; (user's program) EOP ORG 0XFFF JBC 0X0D,4
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
* 27
EM78452
8-Bit Microcontroller
For Slaver
ORG 0X0 INITI: JMP INIT ORG 0X2 INTERRUPT: MOV A,@0X55 MOV 0X06,A MOV A,@0B11100110 MOV 0X0D,A BS 0X0D,4 MOV A,@0X00 MOV 0X0B,A BS 0X0D,4 NOP JBC 0X0D,4 JMP $-2 BS 0X0D,4 BC MOV MOV XOR JBS JMP JMP 0X03,2 A,0X0A 0X06,A A,@0XAA 0X03,2 SPI $-6
; Interrupt address ; Show a signal at Port 6 when entering ; interrupt ; Enable SPI, /SS disabled ; Keep SSE at 1 to wait for SCK signal in order to shift data ; Move 00 to write buffer in order to keep ; master's read buffer as 00 ; Keep SSE at 1 to wait for SCK signal in ; order to shift data ; Polling loop for checking SPI ; transmission completed ; Keep SSE at 1 to wait for SCK signal in ; order to shift data
; Read master's data from read buffer ; Check pass signal from read buffer
28 *
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
ORG 0X30
INIT:
CLRA IOW 0X05 IOW 0X06 MOV 0x05,A MOV 0X06,A MOV A,@0XFF IOW 0X08 MOV A,@0B11001111 CONTW MOV A,@0B00010001 IOW 0X0E MOV A,@0B00000010 IOW 0XF ENI MOV A,@0B00110111 IOW 0x09 BC 0X3F,1 NOP JBS 0X3F,1 JMP $-2 JMP INTERRUPT SPI: BS 0X0D,4 WDTC MOV A,@0X0F MOV 0X06,A JBC 0X08,1 JMP SPI MOV A,@0X5A MOV 0X0B,A NOP JBC 0X0D,4 JMP $-2 BS 0XD,4 NOP NOP MOV A,@0XF0
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
; Set prescaler for WDT ; Disable wakeup function ; Enable external interrupt
; Clear RBFIF flag ; Polling loop for checking interrupt ; occurrences
; Keep SSE enabled as long as possible ; Show a signal when entering SPI loop ; Choose P81 as a signal button ; Move 5A into write buffer when P81 button ; is pushed
; Polling loop for checking SPI ; transmission completed
; Display at Port6 when P81 button is pushed
* 29
EM78452
8-Bit Microcontroller
MOV 0X06,A MOV A,@0X00 MOV 0X0B,A NOP JBC 0X0D,4 JMP $-2 BS 0X0D,4 JMP INITI BC 0x0C,1 NOP JMP SPI DELAY:
; Send a signal to master to prevent ; infinite loop
; (user's program)
EOP ORG 0XFFF BS 0x0C,7
5.6 Timer 1
5.6.1 Overview
Timer 1 (TMR1) is an 8-bit clock counter with programmable prescaler. The TMR1 is in SPI baud rate clock generator mode (SBRS0, SBRS1and SBRS2 a1l set to 1) and then SPI control register Bit 4 (SSE) is set to "1". Timer 1 will be enabled automatically without setting TM1E. TMR1 can be read and written to, and cleared on any reset conditions.
5.6.2 Function Description
Fig. 5-14 shows Timer 1 block diagram. Each signal and block is described as follows:
Set predict value TM1E
0
TMR1 value
1
Set TM1IF TMR1 up Counter Overflow
In SPI baud generator mode ?
Yes
Interrupt and SPI clock output
T1ROS
Prescaler 1:1~1:16
No Interrupt
OSC / 4
Fig. 5-14 Timer 1 Block Diagram
30 *
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
OSC/4: Input clock. Prescaler: Option of 1:1, 1:4, 1:8, and 1:16 defined by T1P1 and T1P2 (T1CON<1, 0>). It is cleared when a value is written to TMR1 or T1CON, and during any kind of reset as well. TMR1: Timer 1 register. TMR1 increases until it overflows, and then resets to 0. If it is in the SPI baud rate generator mode, its output is fed as a shifting clock. TMR1 register; increases until it overflows, and then reloads the predicted value. If a value is written to Timer 1, the predicted value and TMR1 value will be the set value. However, If TRIOS is set to "1" and value is read from TMR1, the value will be TMR1 direct value. Or else, TRIOS is set to "0" and the value is read from TMR1, the value will be TMR1 predicted value.
5.6.3 Programming the Related Registers
The related registers of the defining TMR1 operation are shown in Table 4 and Table 5 Table 3 Related Control Registers of the TMR1
Address 0x0C 0x0F Name SPIS/RC INTC/IOCF Bit 7 DORD 0 Bit 6 TD1 0 Bit 5 TD0 0 Bit 4 T1ROS 0 Bit 3 OD3 TM1IE Bit 2 OD4 SPIIE Bit 1 EXIE Bit 0 RBF TCIE
Table 4 Related Status/Data Registers ofTMR1
Address 0X0E 0x0C Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TMR1/RE TMR17 TMR16 TMR15 TMR14 TMR13 TMR12 TMR11 TMR10 T1CON/IOCC 0 0 0 0 0 TM1E TM1P1 TM1P0
TMR1: Timer 1 Register TMR17~TMR10 are bit set of Timer1 register and it increases until the value matches PWP and then it resets to 0. T1ROS (Bit 3): Timer Read Buffer Select Bit 0: Read Value from Timer 1 Preset Register 1: Read Value from Timer 1 Counter Register. T1CON: Timer 1 Control Register Bit 2 (TM1E): Timer1 enable bit Bit 1 (TM1P1) and Bit 0 (TM1P): Timer 1 prescaler for FSCO
TM1P1 0 0 1 1 Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
TM1P0 0 1 0 1
Prescaler Rate 1:1 1:4 1:8 1:16 * 31
EM78452
8-Bit Microcontroller
5.7 Reset and Wake-up
A reset is initiated by (1) Power-on reset, or (2) /RESET pin input "low", or (3) WDT timeout. (if enabled)
VDD
Oscillator
D Q CLK CLR
CLK
Poweron Reset Voltage Detector
WDTE
WDT timeout
WDT
Setup Time
Reset
Fig. 5-15 Block Diagram of Reset
The EM78452 POR voltage range is between 1.2V~2.0V. Under customer application, when power is OFF, the Vdd must drop below 1.2V and remains OFF for 10s before power can be switched ON again. This way, the EM78452 will reset and work normally. The extra external reset circuit will work well if Vdd can rise at very fast speed (50 ms or less). However, in most cases where critical applications are involved, extra devices are required to assist in solving the power-up problem. The device is kept in a RESET condition for a period of approx. 18ms 2 (one oscillator start-up timer period) after the reset is detected and Fig. 5-15 is the block diagram of reset. Once the RESET occurs, the following functions are performed. The oscillator is running, or will be started. The Program Counter (R2) is set to all "1". When power is switched on, Bits 5~6 of R3 and the upper 2 bits of R4 are cleared. All I/O port pins are configured as input mode (high-impedance state). The Watchdog timer and prescaler are cleared.
2
Vdd = 5V, set up time period = 16.20ms 30% Vdd = 3V, set up time period = 18.0ms 30%
32 *
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
The Watchdog timer is enabled if the Code Option bit ENWDT is "1". The CONT register is set to all "1" except for Bit 6 (INT flag). Bits 3 and 6 of the IOCE register are cleared, Bits 0, 4~5 of the IOCE register are set to "1". Bit 0 of R3F and Bit 0 of the IOCF registers are cleared. The sleep mode (power down) is achieved by executing the SLEP instruction (named as Sleep 1 MODE). While entering sleep mode, the WDT (if enabled) is cleared but keeps on running. The controller is awakened by WDT timeout (if enabled), and it will cause the controller to reset. The T and P flags of R3 are used to determine the source of the reset (wake-up). In addition to the basic Sleep 1 Mode, the EM78452 has another sleep mode (caused by clearing "SLPC" bit of IOCE register, designated as Sleep 2 Mode). In the Sleep 2 Mode, the controller can be awakened by:
(a) Any of the wake-up pin(s) is set to "0." (Refer to Fig. 5-16). Upon waking, the controller will continue to execute the program in-line. In this case, before entering Sleep 2 Mode, the wake-up function of the trigger sources (P60~P67, P74~P75, and P90~P91) should be selected (e.g. input pin) and enabled (e.g. pull-high, wake-up control). One caution should be noted is that after waking up, the WDT is enabled if the Code Option bit ENWDT is "1". The WDT operation (to be enabled or disabled) should be appropriately controlled by software after waking up. (b) WDT time-out (if enabled) or external reset input on /RESET pin will trigger a controller reset.
Table 5 Usage of Sleep and Sleep 2 Mode
Usage of Sleep and Sleep2 Mode SLEEP2 (a) Before Sleep 1. Set Port6 or P74 or P75 or P90 or P91 Input 2. Enable Pull-high and set WDT prescaler over 1:1 (Set CONT.7 and CONT.3 ~ CONT.0) 3. Enable Wake-up ( IOCE.0) 4. Execute Sleep 2 (Set IOCE.4) (b) After Wake-up 1. Next instruction 2. Disable Wake-up 3. Disable WDT (Set IOCE.5) (b) After Wake-up 1. Reset (a) Before Sleep 1. Execute SLEP instruction SLEEP
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
* 33
EM78452
8-Bit Microcontroller
If Port6 Input Status Changed Wake-up is used to wake-up the EM78452 (Case [a] above), the following instructions must be executed before entering Sleep 2 mode: MOV IOW MOV CONTW MOV IOW After Wake-up NOP MOV IOW A, @ xx01xxx1b IOCE ; Disable Port 6 wake-up function; ; Disable WDT A, @xx00xxx0b IOCE ; Enable Port 6 wake-up function, Enable ; Sleep 2 A, @11111111b IOC6 A, @0xxx1010b ; Set Port6 pull-high, WDT prescaler, ; prescaler must set over 1:1 ; Set Port 6 input
After waking up from the Sleep 2 mode, WDT is automatically enabled. The WDT enabled/disabled operation after waking up from Sleep 2 mode should be properly defined in the software. To avoid a reset from occurring when the Port 6 "Input Status Changed Interrupt" enters into an interrupt vector or is used to wake-up the MCU, the WDT prescaler must be set above the ratio of 1:1.
34 *
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
Table 6 Summary of the Initialized Values for Registers
Address Name Reset Type Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name 0x04 R4 (RSR) Power-on /RESET and WDT Wake-up from Pin Change Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
Bit 7 C57 1 1 P C67 1 1 P C77 1 1 P C87 1 1 P C97 1 1 P
/PHEN
Bit 6 C56 1 1 P C66 1 1 P C76 1 1 P C86 1 1 P C96 1 1 P /INT 0 P P U P P 0 0 P 1 1 **P PS1 0 0 P 0 0 P
Bit 5 C55 1 1 P C65 1 1 P C75 1 1 P C85 1 1 P C95 1 1 P 1 1 P U P P 0 0 P 1 1 **P PS0 0 0 P U P P
Bit 4 C54 1 1 P C64 1 1 P C74 1 1 P C84 1 1 P C94 1 1 P 1 1 P U P P 0 0 P 1 1 **P T t t t U P P
Bit 3 C53 1 1 P C63 1 1 P C73 1 1 P C83 1 1 P C93 1 1 P PAB 1 1 P U P P 0 0 P 1 1 **P P t t t U P P
Bit 2
Bit 1
Bit 0
N/A
IOC5
N/A
IOC6
N/A
IOC7
N/A
IOC8
N/A
IOC9
N/A
CONT
0x00
R0 (IAR)
0x01
R1 (TCC)
0x02
R2 (PC)
0x03
R3 (SR)
1 1 P U P P 0 0 P 1 1 **P GP 0 0 P 0 0 P
C52 C51 C50 1 1 1 1 1 1 P P P C62 C61 C60 1 1 1 1 1 1 P P P C72 C71 C70 1 1 1 1 1 1 P P P C82 C81 C80 1 1 1 1 1 1 P P P C92 C91 C90 1 1 1 1 1 1 P P P PSR2 PSR1 PSR0 1 1 1 1 1 1 P P P U U U P P P P P P 0 0 0 0 0 0 P P P 1 1 1 1 1 1 **P **P **P Z DC C U U U P P P P P P U P P U P P U P P * 35
RSR.1 RSR.0
EM78452
8-Bit Microcontroller
Address
Name
Reset Type Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name
Bit 7 P57 U P P P67 U P P P77 U P P P87 U P P P97 U P P U P P U P P 0 0 P
CES
Bit 6 P56 U P P P66 U P P P76 U P P P86 U P P P96 U P P U P P U P P 0 0 P
SPIE
Bit 5 P55 U P P P65 U P P P75 U P P P85 U P P P95 U P P U P P U P P 0 0 P
SRO
Bit 4 P54 U P P P64 U P P P74 U P P P84 U P P P94 U P P U P P U P P 0 0 P 0 0 P 0 0 P U U U
Bit 3 P53 U P P P63 U P P P73 U P P P83 U P P P93 U P P U P P U P P 0 0 P 0 0 P 0 0 P T1IF 0 0 P
Bit 2 P52 U P P P62 U P P P72 U P P P82 U P P P92 U P P U P P U P P OD4 0 0 P 0 0 P 0 0 P 0 0 P
Bit 1 P51 U P P P61 U P P P71 U P P P81 U P P P91 U P P U P P U P P 0 0 P 0 0 P 0 0 P 0 0 P
Bit 0 P50 U P P P60 U P P P70 U P P P80 U P P P90 U P P U P P U P P RBF 0 0 P 0 0 P 0 0 P TCIF 0 0 P
0x05
R5 (P5)
0x06
R6 (P6)
0x07
R7 (P7)
0x08
R8 (P8)
0x09
R9 (P9)
SRB7 SRB6 SRB5 SRB4 SRB3 SRB2 SRB1 SRB0
0x0A
RA Power-on (SPIRB) /RESET and WDT Wake-up from Pin Change Bit Name RB Power-on (SPIWB) /RESET and WDT Wake-up from Pin Change Bit Name RC (SPIS) Power-on /RESET and WDT Wake-up from Pin Change Bit Name RD (SPIC) Power-on /RESET and WDT Wake-up from Pin Change Bit Name RE (TMR1) Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change
SWB7 SWB6 SWB5 SWB4 SWB3 SWB2 SWB1 SWB0
0x0B
DORD TD1
TD2 T1ROS OD3
0x0C
SPISE SDOC SBRS2 SBRS1 SBRS0
0x0D
0 0 P 0 0 P U U U
0 0 P 0 0 P U U U
0 0 P 0 0 P U U U
TMR17 TMR16 TMR15 TMR14 TMR13 TMR12 TMR11 TMR10
0x0E
SPIIF EXIF
0x3F
R3F (ISR)
36 *
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
Address
Name
Reset Type Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on
Bit 7 0 0 P S7 1 1 P U U U U U U U P P
Bit 6 0 0 P 1 1 P ODE 0 0 P U U U U P P
Bit 5 0 0 P 1 1 P
Bit 4 0 0 P 1 1 P
Bit 3 0 0 P /PU9 1 1 P
Bit 2 T1E 0 0 P /PU8 1 1 P U U U 0 0 P U P P
Bit 1 0 0 P /PU6 1 1 P U U U 0 0 P U P P
Bit 0 0 0 P /PU5 1 1 P /WUE 1 1 P TCIE 0 0 P U P P
T1P1 T1P0
0x0C
IOCC
0x0D
IOCD
/RESET and WDT Wake-up from Pin Change Bit Name
WTE SLPC ROC 1 1 1 U U U U P P 1 1 1 U U U U P P 0 0 P T1IE 0 0 P U P P
0x0E
IOCE
Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change
SPIIE EXIE
0x0F
IOCF
0x0F~0x3E
GPR
**To execute the next instruction after the "SLPC" bit status of IOCE register being on high-to-low transition.
U: Unknown or don't care P: Previous value before reset
X: Not used t: Check Table 7
-: Not defined
5.7.1 The Status of RST, T, and P of STATUS Register
A reset condition is initiated by the following events: 1. Power-on condition 2. Watchdog timer time-out The values of T and P, listed in Table 7 are used to check how the processor wakes up. Table 8 shows the events that may affect the status of T and P. Table 7 The Values of RST, T and P After RESET
Reset Type Power on WDT during Operating mode WDT wake-up during Sleep 1 mode WDT wake-up during Sleep 2 mode Wake-Up on pin change during Sleep 2 mode T 1 0 0 0 P P 1 P 0 P P
*P: Previous value before reset Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
* 37
EM78452
8-Bit Microcontroller
Table 8 The Status of RST, T and P Being Affected by Events
Event Power on WDTC instruction WDT time-out SLEP instruction Wake-up on pin change during Sleep 2 mode T 1 1 0 1 P P 1 1 *P 0 P
*P: Previous value before reset
5.8 Interrupt
The EM78452 has the following interrupts. 1. /TCC overflow interrupt 2. External interrupt (/INT) 3. Serial Peripheral Interface (SPI) transmission completed interrupt. 4. Timer 1 overflow interrupt. R3F is the interrupt status register, which records the interrupt request in flag bit. IOCF is the interrupt mask register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (if enabled) is generated, it will cause the next instruction to be fetched from address 001H. Once in the interrupt service routine the source of the interrupt can be determined by polling the flag bits in the R3F register. The interrupt flag bit must be cleared by software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts. The flag in the Interrupt Status Register (R3F) is set regardless of the status of its mask bit or the execution of ENI instruction. Note that reading R3F will obtain the output of logic AND of R3F and IOCF (refer to Fig. 5-16). The RETI instruction exits the interrupt routine and enables the global interrupt (execution of ENI instruction). When an interrupt is generated by INT instruction (if enabled), it causes the next instruction to be fetched from address 002H.
38 *
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
/IRQn
PQ R CLK C LQ R3F D
IRQn IRQm RFRD ENI/DISI interrupt
QP D R C CLK QL
IOD IOCFWR
RESET
IOCF
IOCFRD
RFWR
Fig. 5-16 Interrupt Input Circuit
5.9 Oscillator
5.9.1 Oscillator Modes
The EM78452 can only operate in high Crystal oscillator mode.
5.9.2 Crystal Oscillator/Ceramic Resonators (Crystal)
EM78452 can be driven by an external clock signal through the OSCI pin as shown in Fig 5-18. In most applications, pin OSCI and pin OSCO is connected with a crystal or ceramic resonator to generate oscillation. Fig. 5-18 depicts such circuit. Table 9 provides the recommended values of C1 and C2. Since each resonator has its own attribute, user should refer to its specification for appropriate values of C1 and C2. RS, a serial resistor may be necessary for AT strip cut crystal or low frequency mode.
OSCI OSCO
Ext. Clock
Fig. 5-17 Circuit for External Clock Input
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
* 39
EM78452
8-Bit Microcontroller
C1 OSCI XTAL OSCO RS
Fig. 5-18 Circuit for Crystal/Resonator
C2
Table 10 Capacitor Selection Guide for Crystal Oscillator Ceramic Resonators
Oscillator Type Frequency Mode Frequency 455 KHz 1.0 MHz 2.0 MHz 4.0 MHz 455 KHz 1.0 MHz 2.0 MHz 4.0 MHz C1 (pF) 10~150 40~80 20~40 10~30 20~40 15~30 15 15 C2 (pF) 10~150 40~80 20~40 10~30 20~150 15~30 15 15
Ceramic Resonator
HXT
Crystal Oscillator
HXT
Fig. 5-19 Circuit for External R, Internal C Oscillator Mode
5.10 Code Option Register :
Word 0
Bit 5 ENWDT Bit 4 CLKS Bit 3 SPIHSK Bit 2 REN Bit 1 SDOS Bit 0 WUTT
Bit 5 (ENWDT): Watchdog Timer enabled. 0: Enable 1: Disable Bit 4 (CLKS): Clocks of each instruction cycle. 0: Two clocks 1: Four clocks Bit 3 (SPIHSK): SPI handshake enable bit 0: enable SPI handshake function. When this bit is set to "0." In SPI Slave mode, after SPI control register bit 4(SSE) is set to "1" it will send a high level through P91 (SRDY). Inform the "master" that the "Slave" is ready. 1: disable SPI handshake function
40 *
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller Bit 2 (REN): reset pin enable bit 0: enable, P70/reset reset pin 1: disable, P70/reset P70 Bit 1(SDOS): Serial data output status select bit 0: enable, SDOC Function enable., 1: disable, SPI Function, the same as EM78452 waveform. Bit 0 (WUTT): Wake up Trigger Type 0: Wake up trigger method as EM78P156 (Edge Trigger) 1: Wake up trigger as before (Low Level Trigger).
5.11 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and it includes one or more operands. All instructions are executed within one single instruction cycle (consisting of 2 oscillator periods), unless the program counter is changed by:
(a) Executing the instruction "MOV R2,A", "ADD R2,A", "TBL", or any other instructions that write to R2 (e.g. "SUB R2,A", "BS R2,6", "CLR R2", ). (b) execute CALL, RET, RETI, RETL, JMP, Conditional skip (JBS, JBC, JZ, JZA, DJZ, DJZA) which were tested to be true.
Under these cases, the execution takes two instruction cycles. In addition, the instruction set has the following features: (1). Every bit of any register can be set, cleared, or tested directly. (2). The I/O register can be regarded as general register. That is, the same instruction can operate on I/O register.
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
* 41
EM78452
8-Bit Microcontroller
Convention: R = Register designator that specifies which one of the registers (including operation and general purpose
registers) is to be utilized by the instruction.
b = Bit field designator that selects the value for the bit located in the register R and which affects the
operation.
k = 8 or 10-bit constant or literal value
Binary Instruction 0 0000 0000 0000 0 0000 0000 0001 0 0000 0000 0010 0 0000 0000 0011 0 0000 0000 0100 0 0000 0000 rrrr 0 0000 0001 0000 0 0000 0001 0001 0 0000 0001 0010 0 0000 0001 0011 0 0000 0001 0100 0 0000 0001 rrrr 0 0000 0010 0000 0 0000 01rr rrrr 0 0000 1000 0000 0 0000 11rr rrrr 0 0001 00rr rrrr 0 0001 01rr rrrr 0 0001 10rr rrrr 0 0001 11rr rrrr 0 0010 00rr rrrr 0 0010 01rr rrrr 0 0010 10rr rrrr 0 0010 11rr rrrr 0 0011 00rr rrrr 0 0011 01rr rrrr 0 0011 10rr rrrr 0 0011 11rr rrrr 0 0100 00rr rrrr 0 0100 01rr rrrr 42 *
Hex 0000 0001 0002 0003 0004 000r 0010 0011 0012 0013 0014 001r 0020 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr
Mnemonic NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R TBL MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R
Operation No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC, Enable Interrupt CONT A IOCR A R2+A R2, Bits 8~9 of R2 unchanged AR 0A 0R R-A A R-A R R-1 A R-1 R A VR A A VR R A&RA A&RR ARA ARR A+RA A+RR RA RR
Status Affected None C None T, P T, P None 1 None None None None None None 1 Z, C, DC None Z Z Z, C, DC Z, C, DC Z Z Z Z Z Z Z Z Z, C, DC Z, C, DC Z Z
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
Binary Instruction 0 0100 10rr rrrr 0 0100 11rr rrrr 0 0101 00rr rrrr 0 0101 01rr rrrr 0 0101 10rr rrrr 0 0101 11rr rrrr 0 0110 00rr rrrr 0 0110 01rr rrrr 0 0110 10rr rrrr 0 0110 11rr rrrr 0 0111 00rr rrrr 0 0111 01rr rrrr 0 0111 10rr rrrr 0 0111 11rr rrrr 0 100b bbrr rrrr 0 101b bbrr rrrr 0 110b bbrr rrrr 0 111b bbrr rrrr 1 00kk kkkk kkkk 1 01kk kkkk kkkk 1 1000 kkkk kkkk 1 1001 kkkk kkkk 1 1010 kkkk kkkk 1 1011 kkkk kkkk 1 1100 kkkk kkkk 1 1101 kkkk kkkk 1 1110 0000 0010 1 1111 kkkk kkkk
1 2 3
Hex 04rr 04rr 05rr 05rr 05rr 05rr 06rr 06rr 06rr 06rr 07rr 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E02 1Fkk
Mnemonic COMA R COM R INCA R INC R DJZA R DJZ R RRCA R RRC R RLCA R RLC R SWAPA R SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k INT ADD A,k
Operation /R A /R R R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1), R(0) C, C A(7) R(n) R(n-1), R(0) C, C R(7) R(n) A(n+1), R(7) C, C A(0) R(n) R(n+1), R(7) C, C R(0) R(0-3) A(4-7), R(4-7) A(0-3) R(0-3) R(4-7) R+1 A, skip if zero R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1 [SP], (Page, k) PC (Page, k) PC kA AkA A&kA AkA k A, [Top of Stack] PC k-A A PC+1 [SP], 002H PC k+A A
Status Affected Z Z Z Z None None C C C C None None None None None 2 None 3 None None None None None Z Z Z None Z, C, DC None Z, C, DC
Note: This instruction is applicable to IOC5~IOC9, IOCD ~ IOCF only.
This instruction is not recommended for RF operation. This instruction cannot operate on R3F.
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
* 43
EM78452
8-Bit Microcontroller
5.12 Timing Diagrams
AC Test Input/Output W aveform
2.4 2.0 0.8 0.4
TEST POINTS
2.0 0.8
AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Timing measurements are made at 2.0V for logic "1",and 0.8V for logic "0".
RESET Timing (CLK="0")
NOP
Instruction 1 Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins CLK
TCC
Ttcc
44 *
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
6
Absolute Maximum Rating
Items Temperature under bias Storage temperature Input voltage Output voltage Operating Frequency (2clk) 0C -65C -0.3V -0.3V DC Rating to to to to to 70C 150C +6.0V +6.0V 20MHz
7
Electrical Characteristics
7.1 DC Characteristic
Ta=25C, VDD=5V5%, VSS=0V
Symbol Parameter Crystal VDD to 1.8V FXT Crystal VDD to 3.3V Crystal VDD to 5V IIL VIH1 VIL1 VIHX1 VILX1 VIHT1 VILT1 VIH2 VIL2 VIHX2 VILX2 Input Leakage Current Input High Voltage VDD=5V) Input Low Voltage (VDD=5V) Clock Input High Voltage (VDD=5V) Clock Input Low Voltage (VDD=5V) Input high threshold voltage (Schmitt trigger) Input low threshold voltage (Schmitt trigger) Input High Voltage (VDD=3V) Input Low Voltage (VDD=3V) Clock Input High Voltage (VDD=3V) Clock Input Low Voltage (VDD=3V) Output High Voltage VOH1 (Ports 5, 6, 8, P74~P77, P90~P92, P95~P97,) Output High Voltage (P70~P72) Output High Voltage (P93/SDO, P94/SCK) S7=1 (IOCD Register Bit 7), IOH = -9.0mA S7=0 (IOCD Register Bit 7), IOH = -12.0mA IOH = -12.0mA 2 2.4 2.4 2.4 - - - V - - V IOH = -12.0mA 2.4 - - V OSCI OSCI OSCI OSCI P70/RESET pin P70/RESET pin - - VIN = VDD, VSS - - Two clocks Condition Min DC DC DC - 2.0 - 2.5 - 2.0 - 1.5 - 1.5 - Typ - - - - - - - - - - - - - - Max 4 16 20 1 - 0.8 - 1.0 - 0.8 - 0.4 - 0.6 A V V V V V V V V V V MHz Unit
VOH2
VOH3
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
* 45
EM78452
8-Bit Microcontroller
Symbol
Parameter Output Low Voltage
Condition
Min -
Typ -
Max
Unit
VOL1
(Ports 5, 6, 8, P74~P77, P90~P92, P95~P97) Output Low Voltage (P70~P72) Output Low Voltage (P93/SDO, P94/SCK) Output Low Voltage (P74~P77) Pull-high current Pull-high current (P74,P75) Pull high current (P70/RESET) Power down current
IOL =12.0mA S7=1 (IOCD Register Bit 7), IOH = 9.0mA S7=0 (IOCD Register Bit 7), IOH = 12.0mA IOL = 12.0mA IOL = 15.0mA Pull-high active, input pin at VSS Pull-high active, input pin at VSS Pull-high active, input pin at VSS All input and I/O pin at VDD, output pin floating, WDT enabled /RESET="High", Fosc=1.84324MHz (CK2="0"), output pin floating
0.4
V
- - - - -50 - -16 -
0.4 - - - -100 1 -22 -
0.8 V 0.4 0.4 0.4 -240 - -29 V - A mA A A
VOL2
VOL3 VOL4 IPH IPH2 IPH3
ISB
10
ICC
Operating supply current
-
-
3
mA
6.2 AC Characteristic
Ta=0C~70C, VDD=5V5%, VSS=0V
Symbol Dclk Tins Ttcc Twdt Tdrh Parameter Input CLK duty cycle Instruction cycle time (CK2="0") TCC input period Watchdog timer period Device reset hold period Ta=25C Ta=25C RC Type - Conditions - Min 45 500 (Tins+20)/N* - - Typ 50 - - 18 18
3
Max 55 DC - - -
Unit % ns ns ms ms
*N= selected prescaler ratio.
3
Vdd = 5V, set up time period = 16.2ms 30% Vdd = 3V, set up time period = 18.0ms 30%
46 *
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
8
Application Circuit
EM78452
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
* 47
EM78452
8-Bit Microcontroller
APPENDIX A Package Type:
OTP MCU EM78452P EM78452WM EM78452AQ Package Type DIP SOP QFP Pin Count 40 40 44 Package Size 600 mil 450 mil
B Package Information
B.1 40-Lead Plastic Dual in line (PDIP) -- 600 mil
48 *
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
B.2 44-Lead Quad Flat Package (QFP)
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
* 49
EM78452
8-Bit Microcontroller
50 *
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)

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